Computer Hardware – Logic gates, adders, encoders, decoders, multiplexers, universal gates Quiz - ICSE Class 12 Computer Science

Free practice quiz: Computer Hardware – Logic gates, adders, encoders, decoders, multiplexers, universal gates (ICSE Class 12 Computer Science). 60 multiple-choice questions with answers and explanations. Play online, no sign-up needed.

This ICSE Class 12 Computer Science practice quiz has 60 multiple-choice questions on Computer Hardware – Logic gates, adders, encoders, decoders, multiplexers, universal gates, and 59 of them come with an explanation. Try the 5 sample questions below (tap an option to check yourself), then play the full quiz online. No sign-up needed.

Sample questions

1. Which of the following gates cannot be used to construct a full adder circuit?

   1. AND gate
   2. XOR gate
   3. NOT gate
   4. OR gate
   Show answer

   Answer: C. NOT gate

   A full adder requires at least two XOR gates, two AND gates, and two OR gates (or a combination of gates that perform these functions). A NOT gate alone cannot implement the sum or carry logic of a full adder.

2. Consider a 4-bit ripple carry adder. If the carry-in to the least significant bit is 0, and all input bits are 1, what will be the final carry-out of the most significant bit?

   1. 0
   2. 1
   3. Error
   4. Depends on the other inputs
   Show answer

   Answer: B. 1

   Adding four 1s (1111) in binary results in 1111 (decimal 15). This means there is a carry-out of 1 from the most significant bit position, and the sum bits will be 1111. More formally, for 4-bit addition where all bits are 1 and Cin=0: Bit 0: 1+0 = 1, Cout0=0. Bit 1: 1+1+Cout0 = 1+1+0 = 10 (binary), Sum1=0, Cout1=1. Bit 2: 1+1+Cout1 = 1+1+1 = 11 (binary), Sum2=1, Cout2=1. Bit 3: 1+1+Cout2 = 1+1+1 = 11 (binary), Sum3=1, Cout3=1. The final carry-out (Cout3) is 1.

3. Consider the expression Y = (A+B)(A'+C). If implemented using only NAND gates, how many NAND gates are theoretically needed to implement this expression directly?

   1. 3
   2. 4
   3. 5
   4. 6
   Show answer

   Answer: C. 5

   First, simplify the expression: Y = (A+B)(A'+C) = AA' + AC + BA' + BC = 0 + AC + BA' + BC = AC + BA' + BC. This can be further simplified or implemented directly. Let's aim to implement it using NANDs. (A+B) can be (A'B')'. A'+C can be (A''C')'. Y = ((A+B)' + (A'+C)')'. This requires 4 NAND gates for (A+B)' and (A'+C)' and then a NOR (which is a NAND for inversion). Let's re-evaluate. Y = AC + A'B + BC. Using Karnaugh maps or Boolean algebra, we might get a simpler form. However, let's convert the original expression. (A+B) = NAND1 (inputs A,B), then NAND2 (inverter on output). A'+C = NAND3 (inputs A,A), then NAND4 (inputs output of NAND3, C). Now we have (A+B) and (A'+C). To OR them with NANDs: ((A+B)' . (A'+C)')'. This requires two more NANDs. Total: 2 for first term, 2 for second, 2 for OR. If (A+B) is made of 2 NANDs, and (A'+C) is made of 2 NANDs (one inverter for A, then NAND with C), then we need to OR these results. Y = (A+B) OR (A'+C). Using NANDs: (A+B) = (A'B')'. A'+C = (A''C')'. Y = ((A+B)' . (A'+C)')'. Let's implement A+B using 2 NANDs: (A.A)' is A'. A'.B is not direct. A+B = (A'B')'. A'+C. Let's try another way. Y = AC + A'B + BC. Using NANDs: AC requires a NAND and an inverter, so 2. A'B requires an inverter for A, then NAND with B, then inverter: 3. BC needs 2 NANDs. This is getting complex. Standard conversion of (A+B)(A'+C) into NANDs. (A+B) is (A'B')'. (A'+C) is (A''C')'. Let's use a 5-NAND implementation: NAND1(A,B) -> (AB)'. NAND2(output1, output1) -> A+B. NAND3(A,A) -> A'. NAND4(output3,C) -> (A'C)'. NAND5(output2, output4) -> ((A+B)' . (A'C)')'. This is (A+B) + (A'C). The correct expression is (A+B)(A'+C). Let's convert it to NANDs. Y = (A+B)(A'+C) = (AB)' + (A'C)'. Using NANDs: (A+B) = (A'B')'. A'+C = (A''C')'. Let's convert Y = AC + A'B + BC. Using NAND gates: A'B requires 3 NANDs (A', A'B, (A'B)' ). This is incorrect. A' requires 1 NAND gate. A'B requires 2 NAND gates: NAND(A,A)=A', NAND(A',B) = (A'B)'. This is not XOR. Y = A.C + B.A' + B.C. Using 5 NAND gates for Y = AC + A'B + BC: (A' requires NAND(A,A)). Let's simplify Y = (A+B)(A'+C) = AA' + AC + BA' + BC = AC + A'B + BC. Consensus theorem: Y = AC + A'B + BC = AC + A'B. Now, to implement AC + A'B using NANDs. AC = ( (AC)' )'. A'B = ( (A'B)' )'. Y = ( (AC)' )' + ( (A'B)' )' = ( (AC)'.(A'B)' )'. This requires: NAND1(A,C) -> (AC)'. NAND2(output1, output1) -> AC. NAND3(A,A) -> A'. NAND4(output3, B) -> (A'B)'. NAND5(output2, output4) -> ((AC)'.(A'B)')'. This gives Y. So 5 NAND gates are needed.

4. What is the minimum number of NOR gates required to implement a 2-input AND gate?

   1. 2
   2. 3
   3. 4
   4. 1
   Show answer

   Answer: B. 3

   To implement an AND gate using NOR gates: A AND B = ((A+B)')'. First, get A+B using a NOR gate (N1). Then invert the output of N1 using another NOR gate with inputs tied together (N2). This gives (A+B)''. However, to get A AND B, we need to realize it as ((A'+B)')'. Let's use the fact that NOR is universal. A.B = ((A+B)')'. We need to implement (A+B) first. This can be done with a NOR gate: A NOR B = (A+B)'. Then, to invert this, we can use another NOR gate with its inputs tied together: ((A+B)')'. This requires 2 NOR gates. Wait, that's for A+B. For A.B: A.B = (A'+B')'. Implement A' using NOR(A,A). Implement B' using NOR(B,B). Then NOR these two results: NOR(NOR(A,A), NOR(B,B)). This requires 3 NOR gates.

5. A 4-to-1 multiplexer is used to select one of four inputs (D0, D1, D2, D3) based on two select lines (S1, S0). If the select lines are used to enable specific outputs of a 3-to-8 decoder, how would this typically be configured to achieve the multiplexer function?

   1. The outputs of the decoder are connected to the data inputs of the multiplexer.
   2. The data inputs of the multiplexer are connected to specific outputs of the decoder, controlled by the select lines.
   3. The select lines of the multiplexer are connected to the select lines of the decoder.
   4. The decoder's select lines are used to enable the data inputs of the multiplexer.
   Show answer

   Answer: C. The select lines of the multiplexer are connected to the select lines of the decoder.

   To implement a multiplexer's selection function using a decoder, the select lines of both the multiplexer and the decoder are connected together. The decoder then generates unique enabling signals for each of its output lines, corresponding to the select line combinations. These decoder outputs can then be used to control which data input is routed to the multiplexer's output. For a 4-to-1 MUX using a 3-to-8 decoder, you would connect the MUX select lines (S1, S0) to the lower two select lines of the decoder (e.g., A and B), and the decoder's outputs (corresponding to the select inputs) would be used to enable the data inputs of the MUX. A common implementation would have the MUX's data inputs connected to the decoder outputs through AND gates (which are part of the MUX's internal logic). However, the core idea is that the select lines drive the decoding logic.

More questions in this quiz

Answers and explanations are in the full quiz.

1. A 3-to-8 decoder with active-HIGH outputs will have how many output lines?
2. Which universal gate can be used to implement all other basic logic gates (AND, OR, NOT)?
3. What is the primary function of a multiplexer (MUX)?
4. If the inputs to a 2-to-4 decoder are A=1 and B=0, and the output is active HIGH, which output line will be HIGH?
5. Which logic gate produces an output of 1 only when an odd number of its inputs are 1?
6. Consider a full adder. If the inputs are A=1, B=1, and Cin=1, what are the Sum and Carry-Out (Cout) respectively?
7. A 4-to-1 multiplexer has select lines S1 and S0. If S1=0 and S0=1, which input line will be connected to the output?
8. How many NAND gates are required to implement a 3-input AND gate?
9. What is the output of a NOR gate if its inputs are A=1 and B=0?
10. A priority encoder assigns a higher priority to:
11. Which type of encoder generates a Gray code output from a binary input?
12. Which of the following logic expressions can be implemented using only NAND gates?
13. A 1-to-4 Demultiplexer (DEMUX) takes a single data input and distributes it to one of four possible output lines, controlled by select lines. If the select lines are S1=1 and S0=0, which output line will receive the data input?
14. What is the minimum number of 2-input NAND gates required to implement a 2-input XOR gate?
15. Which of the following statements about a half-adder is FALSE?
16. For a 4-to-10 decoder with active-LOW outputs, if the input is decimal 7, which output line will be LOW?
17. Which is the correct logic expression for the output of a 4-input multiplexer with data inputs D0, D1, D2, D3 and select lines S1, S0?
18. The function of an encoder is to:
19. Which operation is NOT directly performed by a standard full adder?
20. A 1-to-8 decoder takes 1 input line and produces 8 output lines. To uniquely address all 8 outputs, how many select lines are required?
21. What is the output of a NOR gate if its inputs are connected together, acting as an inverter, and the input is 0?
22. If a 4-input priority encoder has inputs P0, P1, P2, P3, and P2 and P3 are active, what will be the binary output code?
23. A full adder adds three bits: A, B, and Cin. What are the logic expressions for the Sum (S) and Carry-Out (Cout)?
24. Which of the following is NOT a property of Gray codes?
25. How many 2-to-1 multiplexers are required to build a 4-to-1 multiplexer?
26. What is the output of a 7-input encoder that has input line 4 active?
27. Consider a circuit that implements the function Y = (A.B)' . (A+C)'. If this circuit is implemented using only NAND gates, what is the minimum number of gates required?
28. Which of the following is the most efficient way to implement a 1-to-8 decoder using only 3-to-8 decoders?
29. A 4-bit magnitude comparator compares two 4-bit binary numbers, A = A3A2A1A0 and B = B3B2B1B0. The output will be HIGH if A > B. Which of the following logic gates would be primarily used in its implementation?
30. What is the primary purpose of a parity generator/checker?
31. To implement a full adder using only NAND gates, what is the minimum number of 2-input NAND gates required?
32. If a 3-to-8 decoder has inputs A (MSB), B, and C (LSB), and the input is binary 101, which output line is activated (assuming active-HIGH outputs)?
33. Which logic gate would be used to implement the 'Select' function in a multiplexer?
34. In a half-subtractor, the difference output is equivalent to:
35. A 1-to-N decoder generates N unique output lines. For a 1-to-16 decoder, how many select lines are needed?
36. Which is the most complex logic gate among the following in terms of internal circuitry for standard TTL implementations?
37. Consider a 4-input multiplexer. If the select lines are S1=1 and S0=0, and the data inputs are D0=0, D1=1, D2=0, D3=1, what is the output Y?
38. A priority encoder is used in a system where multiple interrupt requests can occur simultaneously. Which of the following correctly describes its function in this context?
39. What is the Boolean expression for a full adder's Carry-Out (Cout) if inputs are A, B, and Cin?
40. Which of the following is an example of a 2-bit binary to Gray code converter's truth table?
41. A 1-of-16 decoder has 4 select inputs. If these select inputs are connected to the outputs of a 2-bit binary to 2-bit Gray code converter, what is the pattern of the decoder's activated outputs?
42. Which of the following circuits can be constructed using only NAND gates?
43. Consider a 4-bit ripple carry adder. If the carry-in to the first full adder is 0, and we are adding 1011 (B) to 0101 (A), what is the carry-out from the second full adder (which adds the second LSBs)?
44. What is the minimum number of 2-input NOR gates required to implement a 2-input OR gate?
45. Which type of encoder is used to convert BCD (Binary Coded Decimal) input into a 7-segment display code?
46. What is the minimum number of 2-input NAND gates required to implement a 3-input OR gate?
47. Which statement is TRUE about a Full Adder built with 2-input XOR and AND gates?
48. Consider a 16-to-1 multiplexer. How many select lines are required, and how many data inputs are there?
49. Which of the following is NOT a type of encoder?
50. How many 2-input NOR gates are needed to implement a 2-input XNOR gate?
51. In a 3-bit synchronous counter, if the clock pulses are applied, what determines the sequence of states?
52. A 2-to-4 decoder with active-LOW outputs has an enable input. If the enable input is LOW, what will be the state of the outputs?
53. What is the primary function of a multiplexer in digital systems?
54. Which combination of logic gates can be used to form a 1-bit full adder circuit?
55. What does the term 'universal gate' refer to in digital logic?

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