Computer Hardware – System architecture, processor, memory types Quiz - ICSE Class 11 Computer Science

Free practice quiz: Computer Hardware – System architecture, processor, memory types (ICSE Class 11 Computer Science). 52 multiple-choice questions with answers and explanations. Play online, no sign-up needed.

This ICSE Class 11 Computer Science practice quiz has 52 multiple-choice questions on Computer Hardware – System architecture, processor, memory types, and 52 of them come with an explanation. Try the 5 sample questions below (tap an option to check yourself), then play the full quiz online. No sign-up needed.

Sample questions

1. Which component of a CPU is primarily responsible for executing instructions by performing arithmetic and logical operations?

   1. Control Unit
   2. Arithmetic Logic Unit (ALU)
   3. Registers
   4. Cache Memory
   Show answer

   Answer: B. Arithmetic Logic Unit (ALU)

   The Arithmetic Logic Unit (ALU) is a fundamental part of the CPU that carries out all arithmetic operations (like addition, subtraction, multiplication, division) and logical operations (like AND, OR, NOT, XOR). The Control Unit manages the flow of data and instructions, while registers are small, high-speed storage locations within the CPU, and cache memory is a type of memory that stores frequently accessed data.

2. What is the key difference between synchronous and asynchronous memory?

   1. Synchronous memory is faster than asynchronous memory.
   2. Synchronous memory is volatile, while asynchronous memory is not.
   3. Synchronous memory operates in lockstep with the system clock, while asynchronous memory does not.
   4. Asynchronous memory requires fewer pins on the interface.
   Show answer

   Answer: C. Synchronous memory operates in lockstep with the system clock, while asynchronous memory does not.

   Synchronous memory (like SDRAM) uses the system clock to time its data transfers, allowing for predictable and faster operation. Asynchronous memory (like older DRAM or SRAM) does not rely on a system clock for data transfer timing; instead, it uses control signals to indicate when data is ready. While synchronous memory is generally faster, this is a consequence of its clock synchronization, not the defining difference. Volatility and pin count are not the primary distinguishing factors.

3. What is the role of the System Bus?

   1. To manage the graphical display output
   2. To facilitate communication between CPU, memory, and peripherals
   3. To perform floating-point calculations
   4. To store the operating system files
   Show answer

   Answer: B. To facilitate communication between CPU, memory, and peripherals

   The System Bus is a collective term for the buses that connect the major components of a computer. It typically consists of the data bus, address bus, and control bus, enabling information exchange between the CPU, memory, and I/O devices. Graphics output is handled by the GPU, calculations by the ALU, and OS files are stored on secondary storage.

4. What is the purpose of the Accumulator register in a CPU?

   1. To hold the memory address of the next instruction.
   2. To store the results of arithmetic and logic operations.
   3. To temporarily hold data being transferred between memory and CPU.
   4. To manage the data bus.
   Show answer

   Answer: B. To store the results of arithmetic and logic operations.

   The Accumulator is a special register within the CPU that holds the operands for arithmetic and logic operations and stores the results of these operations. The Program Counter holds the address of the next instruction. General registers might hold temporary data, and the Memory Buffer Register (MBR) holds data being transferred.

5. What is the concept of 'instruction-level parallelism' (ILP)?

   1. The ability of a CPU to execute multiple instructions from different programs simultaneously.
   2. The ability of a CPU to execute multiple instructions from the same program simultaneously.
   3. The process of converting high-level code into machine code.
   4. The management of data flow between CPU and memory.
   Show answer

   Answer: B. The ability of a CPU to execute multiple instructions from the same program simultaneously.

   Instruction-level parallelism (ILP) refers to the degree to which the machine instructions of a computer program can be executed in parallel. Techniques like pipelining, superscalar execution, and out-of-order execution are used to exploit ILP within a single program.

More questions in this quiz

Answers and explanations are in the full quiz.

1. In a pipelined processor, what is the primary benefit achieved by breaking down instruction execution into multiple stages?
2. Consider a superscalar processor. What characteristic allows it to execute multiple instructions in a single clock cycle?
3. What is the primary role of the Memory Management Unit (MMU) in a modern computer system?
4. A system with a 64-bit address bus can theoretically address a maximum of how many unique memory locations?
5. Which type of memory is characterized by its volatility, high speed, and use as the main working memory for a computer?
6. What is the primary function of the Instruction Register (IR) within a CPU's control unit?
7. In the context of memory hierarchy, which level typically offers the largest capacity and slowest access time?
8. What is the purpose of the fetch-decode-execute cycle in a CPU?
9. Consider a system with a memory-mapped I/O scheme. How are I/O devices addressed?
10. What is the primary role of the Program Counter (PC) in a CPU?
11. Which of the following best describes the function of a bus in a computer system?
12. What is a 'cache hit' in the context of CPU cache memory?
13. In a pipelined processor, what is a 'hazard'?
14. Which component is responsible for fetching instructions from memory and coordinating the execution of those instructions?
15. What does the term 'bus width' refer to in a computer system?
16. Which type of memory uses capacitors that need to be periodically refreshed to retain their data?
17. What is the primary function of a 'write-back' policy in CPU caching?
18. A CPU with Hyper-Threading technology (simultaneous multithreading) can:
19. Which of the following memory types has the lowest latency?
20. Consider a CPU using pipelining. If an instruction depends on the result of a previous instruction that is still in an earlier stage of the pipeline, this is known as a:
21. What is the function of the Instruction Decoder in a CPU?
22. Which characteristic of ROM (Read-Only Memory) makes it suitable for storing the BIOS (Basic Input/Output System)?
23. In a superscalar architecture, the ability to execute instructions in an order different from the program sequence, while maintaining the correct program result, is called:
24. What is the primary function of a chipset on a motherboard?
25. Which of the following is a characteristic of SRAM (Static Random-Access Memory)?
26. What is the 'instruction pipeline' concept in CPU design?
27. A 32-bit CPU can address a maximum of how many unique memory locations if each location stores one byte?
28. What is a 'write-through' cache policy?
29. Which of the following describes a 'bus contention' scenario?
30. What is the main advantage of using a multi-level cache hierarchy (e.g., L1, L2, L3 cache)?
31. What is the term for a CPU that can fetch, decode, and execute more than one instruction per clock cycle?
32. Which type of bus is primarily responsible for carrying the address of the memory location or I/O device that the CPU wishes to access?
33. What is the function of the Memory Buffer Register (MBR)?
34. In pipelining, a 'stall' or 'bubble' is introduced when:
35. What does the term 'register renaming' aim to solve in modern CPU architectures?
36. Which component is responsible for managing the transfer of data between the CPU and peripheral devices?
37. What is the primary function of the Cache Controller?
38. Which component is responsible for fetching instructions from memory, decoding them, and directing the execution process?
39. Consider a CPU with a separate memory space for instructions and data. This architecture is known as:
40. Which memory type typically has the highest density (bits per unit area)?
41. What is the purpose of 'speculative execution' in modern CPUs?
42. What is the main advantage of a multi-core processor compared to a single-core processor running at the same clock speed?
43. In a computer system's memory hierarchy, which level typically has the smallest capacity but the fastest access speed?
44. What is the primary purpose of the Control Bus?
45. Which of the following memory types is commonly used for BIOS/UEFI firmware?
46. What is a 'branch prediction buffer' (also known as Branch Target Buffer or BTB) used for in a CPU?
47. In the context of CPU architecture, what is the primary goal of 'pipelining'?

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